1. Field of the Invention
The invention relates to the fabrication of integrated circuit (IC) devices, particularly to dielectric materials, and more particularly to the fabrication of a low-k interlayer dielectric (ILD) layer.
2. Description of the Prior Art
Semiconductor devices are typically joined together to form useful circuits using interconnect structures comprising conductive materials (e.g., metal lines) such as copper (Cu) or aluminum (Al) and dielectric materials such as silicon dioxide (SiO2). The speed of these interconnects can be roughly assumed to be inversely proportional to the product of the line resistance (R), and the capacitance (C) between lines. To reduce the delay and increase the speed, it is desirable to reduce the capacitance (C). This can be done by reducing the dielectric constant k of the dielectric material in the interlayer dielectric (ILD) layers.
Conventional approach for fabricating ILD layer typically includes forming a single layer of silicon dioxide on a substrate. This design is particularly disadvantageous when planarizing process, such as chemical mechanical polishing (CMP) process is conducted to remove the contact metal along with the ILD layer, a major portion of the ILD is lost due to topography loading effect during process and the height of the ILD layer is affected substantially.